Numerous integrated electronic devices require a certain amount of non-volatile memory. Normally, non-volatile memory is available in autonomous banks or cards, external to the chips in which the control and processing functions of the devices are integrated. In many cases, however, processing units must be provided with embedded non-volatile memory integrated in the same chips.
The structure of normal autonomous non-volatile memory cells renders, however, problematical integration in the CMOS manufacturing processes, which are widely exploited for producing the processing and control components. In particular, floating-gate cells normally need an additional level of polysilicon with respect to the CMOS process flows. The larger number of machining steps and masks represents an unjustified increase in cost, especially if it is considered that the required amount of integrated non-volatile memory is frequently modest.
Therefore, non-volatile memory cells with different architectures have been developed, in which the floating gate and the gate regions of all the other integrated transistors are made from a single polysilicon layer. In this way, additional steps and masks are avoided, and the integration in the CMOS process flow is much more convenient.
The solution most commonly used is represented by cost-effective non-volatile memory cells, each of which uses a first selection MOS transistor, a second MOS transistor for program, erase, and read operations, and a third MOS transistor for capacitively coupling the floating gate with a region or a control line. Programming of cost-effective cells is carried out by injection of hot electrons, whereas erasure exploits the Fowler-Nordheim tunneling effect. Memory cells of this type favor programming speed, but penalize both the consumption of current, which is rather high, and the occupation of area. Moreover, the maximum number of erasure and programming cycles is rather limited, and is much lower as compared to the cells of autonomous non-volatile memories.
Fowler-Nordheim memory cells exploit the Fowler-Nordheim effect both for programming and for erasure. The fact of not resorting to the injection of hot electrons enables reduction of the consumption levels during programming as compared to cost-effective cells. Fowler-Nordheim cells enable a higher level of parallelism to be achieved during programming, and are more robust from the standpoint of the maximum number of programming and erasure cycles. However, the area occupied is still rather high and does not depart significantly from that of cost-effective cells that exploit injection of hot electrons.
To overcome this drawback, modified Fowler-Nordheim memory cells have been proposed, in which, however, the reduction of area occupied is at the expense of the robustness in the maximum number of programming and erasure cycles.